1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a method of fabricating trench isolation structure of a semiconductor device.
2. Description of the Related Art
The electrical characteristics or the reliability of a semiconductor device is highly dependent on the technology used to electrically isolate a device formed on a substrate of the semiconductor device. Improper device isolation results in leakage current, and loss of power supplied to a semiconductor chip.
Local oxidation of silicon (hereinafter referred to as “LOCOS”) has been used as the device isolation technology. A typical LOCOS structure is formed by masking an active region with a pattern comprising layers of silicon nitride and pad oxide, implanting ions into an isolation region exposed by the patterned silicon nitride and pad oxide, and growing a thick field oxide in the isolation region. However, the typical LOCOS structure suffers from several problems, namely, the oxidation of silicon laterally under the masking layer which produces a so-called ‘bird's beak’ at the edge of the field oxide, and the lateral diffusion of the channel dopants wherein the dopants encroach the active region. In the case in of a lateral diffusion of channel stop dopants, the dopants attack the active region.
Shallow Trench Isolation (STI) technology has been widely used recently instead of LOCOS technology because of the above-described drawbacks of the LOCOS technology.
However, the STI technology presents problems related to the planarization of the resultant STI structure. That is, it is difficult to form a device isolation layer having a uniform planarity. In particular, the STI technology involves filling a wide trench with an isolation material, and then planarizing the isolation material. The isolation material is over-etched in the planarization process, whereby a so-called, “dishing” phenomenon occurs.
Techniques intended to prevent the dishing phenomenon from occurring in a trench protection layer produced according to STI technology are disclosed in U.S. Pat. No. 6,146,975 and Korean Laid-Open Patent Application No. 2002-0002164.
FIGS. 1 to 4 are cross-sectional views of a semiconductor substrate for schematically illustrating a method of forming a trench isolation structure as disclosed in U.S. Pat. No. 6,146,975, and FIGS. 5 to 9 are cross-sectional views of a semiconductor substrate for schematically illustrating a method of forming a trench isolation structure as disclosed in the Korean Laid-Open Patent Application No. 2002-0002164.
Referring to FIG. 1, a trench 25 is formed by masking a semiconductor substrate 21 with a pad oxide 22 and a mask nitride 23, and etching the underlying region of the semiconductor substrate exposed by the pad oxide 22 and mask nitride 23. Then, a trench insulation layer 27 is formed to fill the trench 25. The trench filler insulation layer 27 has a thickness that is equal to the depth of the trench 25 so as to terminate at the top of the trench 25.
Referring to FIG. 2, a polish stop layer 31 is formed on the trench filler insulation layer 27. A photoresist pattern (not shown) is formed on the polish stop layer 31.
Referring to FIG. 3, the portion of the polish stop layer 31 exposed by the photoresist pattern is etched, so that another portion the polish stop layer 31 remains over the trench 25.
Referring to FIG. 4, a planarization process is carried out on the trench filler insulating layer 27 using the remainder of the polish stop layer 31 and the mask nitride layer 23 as a planarization stopper.
However, if trenches having different widths are formed using this method, the respective portions of the polish stop layer remaining over the trenches have different thicknesses. That is, as shown in FIG. 5, the portion 31a of a polish stop layer left over a narrow trench is thicker than the portion 31b of the polish stop layer left over the wider trench. Accordingly, the planarization process (refer to the dotted line of FIG. 5) leaves the trench filler insulation layer over the mask nitride layer formed on the active region adjacent the narrow trench. Therefore, the mask nitride will remain on the active region even after a subsequent cleaning process intended to remove the mask nitride because the trench filler insulating layer covers the mask nitride during the cleaning process.
Also, the polish stop layer remaining in the trench may be etched during the planarization process because the trench filler insulation layer, which has the thickness corresponding to the depth of the trench, covers the mask nitride layer.
In this case, the polish stop layer could be formed thick to enhance its ability to control the planarization process. However, this technique necessitates that the silicon nitride polish stop layer remain over the trench during the photolithographic process. The thicker the silicon nitride polish stop layer, the greater the reflectivity of the exposure light becomes during the photolithographic process. Thus, a thick silicon nitride polish stop layer makes it difficult to implement the photolithographic process.
Now, another conventional approach will be described with reference to FIG. 6 through FIG. 9.
Referring first to FIG. 6, a trench filler insulation layer 120 is formed to fill a trench ‘T’. Dishing protection layer 130 is formed on the trench filler insulation layer 120.
Next, referring to FIG. 7, an etching process is carried to leave the dishing protection layer 130′ over only the trench T.
Next, referring to FIG. 8, an insulation layer 140 is formed on the trench filler insulation layer 120 and the dishing protection layer 130′. This is to guarantee the efficacy of the subsequent planarization process, i.e., to thereby prevent the dishing protection layer 130′ from being etched.
Referring to FIG. 9, the device isolation is completed by performing the planarization process.
This method entails the forming of an additional insulation layer 140 as compared to the method disclosed in U.S. Pat. No. 6,146,975. Accordingly, the raw cost of the fabricating process is greater than that disclosed in U.S. Pat. No. 6,146,975, and the method is also subject to problems related to the process of forming the additional insulating layer.